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Da ta S he et , V 1. 0, O ct . 20 03
T C 1 91 0
3 2 - B i t S i n g le - C h i p M ic r o c o n t r o l l e r
M i c ro c o n t ro l l e rs
Never
stop
thinking.
Edition 2003-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da ta S he et , V 1. 0, O ct . 20 03
T C 1 91 0
3 2 - B i t S i n g le - C h i p M ic r o c o n t r o l l e r
M i c ro c o n t ro l l e rs
Never
stop
thinking.
TC1910 PRELIMINARY Revision History: Previous Version: Page
2003-10
V 1.0
Subjects (major changes since last revision)
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TC1910
PRELIMINARY TC1910 Features The TC1910 offers a 32 bit TriCore based microcontroller/DSP, which is mainly designed for automotive telematics applications. Due to its high integration, this microcontroller/ DSP offers high system performance at minimized cost. Typical telematics functions processed by RISC-, DSP- and speech- (CODEC) modules are now combined in one component. This combination of dedicated speech peripherals (CODEC) and standard peripherals (SSC/SPI, ASC and IIC), makes this microcontroller/DSP the engine tailored for a wide variety of telematics applications such as navigation, emergency call, speech interface or communication interface. * TriCore CPU/DSP with 4-Stage Pipeline: - 66 MHz max. CPU clock frequency, 50 MHz max. FPI Bus clock frequency. - 32-bit super-scalar TriCore main CPU - 4-GByte unified memory space support - Fast context-switching - Dual 16 x 16 Multiply-accumulate (MAC) unit - 64-bit Local Memory Bus (LMB) - 32-bit Flexible Peripheral Interface Bus (FPI) - 32-bit wide External Bus Unit (EBU) * On-chip memories: - 24 KByte Code Scratch-Pad RAM (CSRAM) - 8 KByte Instruction Cache (ICACHE) - 24 KByte Data Scratch-Pad RAM (DSRAM) - 8 KByte Data Cache (DCACHE) - 64 KByte fast LMB SRAM - 16 KByte FPI SRAM (of which 8 KByte Stand-By SRAM) * Product Specific Peripherals: - 14-bit double CODEC with flexible sample rates and FIFO support - 8 External Interrupt Inputs * Standard Peripherals: - 2 x asynchronous serial interface (ASC) with IrDa-support - 1 SPI-compatible synchronous serial interface - IIC module - 3 x 32 bit timer * General Peripherals: - Real time clock (RTC) - Watchdog timer (WDT) * Clock Generation Unit with PLL * Debug Support: OCDS Level 1 with JTAG interface * Dual voltage supply (1.8V core, 3.3V I/O) * Power saving features * -40C to +85C temperature range * LBGA-208 package
Data Sheet 1 V 1.0, 2003-10
TC1910
PRELIMINARY Block Diagram.
LFI Bridge C O DE C (IIS)
SRA M 6 4 kB
E BU
6 4 -b it L o ca l M e m o ry B u s (L M B ) G P TU PM U 24KB CSRAM 8KB IC A C H E TriCore (T C 1 .3 ) CPS O CDS D ebug/ JTA G DM U 24KB D SRAM 8KB DCACHE
IIC
AS C0
Port C ontrol
AS C1
S SC
3 2-b it F lexible P erip he ra l In te rface (F P I)B u s
S RAM 1 6 kB
R TC
STM
S CU
TC1910
Figure 1
TC1910 Device Block Diagram
Target applications * Bluetooth gateway (host for BT stack e.g. for Handsfree with EC/NR or remote diagnostics) * Stand-alone speech Human Machine Interface * Basic communication gateway * Digital Audio processing (MP3 player, shock proof controller etc.)
Data Sheet
2
V 1.0, 2003-10
TC1910
PRELIMINARY Logic Symbol
PLL_CTRL TE S T CLKOU T HDRST PORST NMI BYPASS XTAL1 XTAL2 XTAL3 XTAL4 VD D O S C 1 VS S O S C 1 VD D O S C 2 VS S O S C 2 VD D P L L VS S P L L VD D VD D P VD D S B VS S G e n e ra l C o n tro l
G P IO /E X Ix, C o d ec B yp ass G P IO IIC, SSC ASC0 ASC1 G P TU
P o rt 0 8 -b it P o rt 1 8 -b it P o rt 2 1 6 -b it P o rt 3 1 6 -b it
10
C O D E C 0 /1 O scilla to rs PLL E xte rn a l B u s TC1910
83
O C D S /JT A G C o n tro l
8
D ig ita l C ircu itry P o w er S u pp ly
VD D _ C O D 0 VS S _ C O D 0 VD D _ C O D 1 VS S _ C O D 1 V R E F_ C O D VG N D _ C O D
CODEC A n a lo g P o w e r S u p p ly
Figure 2
Data Sheet
TC1910 Device Logic Symbol
3 V 1.0, 2003-10
TC1910
PRELIMINARY Pin Configuration
1 A B C D E F G H J K L M N P R T
2
3
4
5 V DD _
R TC
6
7
8 V S S_
PL L
9 V DD _
P LL
10 V D D_
C O D 0 /1
11 VSSA_
C O D 0 /1
12 BY PASS
13 NMI
14 CLK OU T
15 P 2 .3 P 2 .5 IIC _ SDA
16 P 2 .0 P 3 .15 E X IN 7 A B C D E F G H J K L M N P R T
A D 2 0 A D 26 A D 28 A D 2 9 A D 1 7 A D 25 A D 27 A D 3 0 A D 1 3 A D 23 A D 24 A D 3 1 AD9 AD8 AD7 AD5 AD2 EBU CLK BF CLK0 A 17 A 15 A 10 A7 A4 A2 1 A D 21 A D 22 VDD_
PW R
X T A L 1 X T A L2
V S SA
_32K
V D DP _ V SS P _ V D D_
P LL P LL GU A RD
A I0-
A I1 -
A O 1+ A O 0+
A O 0- H R S T E X IN 4 CODE PORS SSC_ C _ D IS T M TSR V DD _
PWR
TM_ T M _ V S S_ V A GN D _ A I1+ C T R L1 X T A L 4 C T R L 0 G U A R D C O D XTAL3 VDDR
V D D _ P LL C T V A RE F_ A I0 + AO1- CE XT O S C I R L _A 0 CO D
S S C _ A S C 0 _ A S C 1_ S C LK RX TX P 3 .11 E X IN 5
A D 18 A D 16 A D 1 9 A D 15 A D 14 A D 1 2 A D 11 A D 10 AD4 AD1 A22 A18 A14 A9 A6 A3 CAS 2 AD3 A23 A20 A16 A12 A8 A5 A0 BC3 3 AD6 AD0 A 21 A 19 A 13 A 11 VDD_
PW R
S S C _ A S C 0 _ IIC _ M RST TX SCL P 2.8 VDD_
PW R2
P 2.9 P 2.2
P 2 .4
VSS_
GND
V SS _
GND
V D D_
P W R2
P 2.1
E X IN 6 P 3 .10
VDD_
PW R
VSS_
GND
V SS _
GND
HS5 HS4 V D D_
P W R2
G P T U . G P T U . G P T U . A S C 1_ 4 5 7 RX GPT U . SC AN G PTU . G PTU . MODE 0 6 3 LR C K M U T E 1 GPTU . GPTU . 2 1
H S 15 VDD_
PW R2
VSS_
GND
V SS _
GND
HS14 HS13
V D D S B E X IN 3 S C L K M U T E 0 P 1.7 RAS BC0 C S 1 C S G LB A D V CS2 CS0 W A IT 7 BAA CS EMU CKE M R /W H S 11 H S 10 ALE HS7 HS6 HS8 HS9 11 HS0 BRK OUT HS2 HS3 12 V DD _
PWR
E X IN 0 E X IN 1 E X IN 2 P 1.4 P 1.0 TD O P 1 .5 P 1 .2 TC K TD I 15 P 1 .6 P 1 .3 P 1 .1 TR ST 16
A1 RD BC2 4
R D /W R C S 6 BC1 CS5 5 CS4 CS3 6
TMS B RK IN
CS CM O V L D E L A Y H S 12 8 9 10
HS1 OCDSE 13 14
T O P V IE W
LBG A 208
Figure 3
TC1910 Pinning
Data Sheet
4
V 1.0, 2003-10
TC1910
PRELIMINARY Pin List Table 0-1 Symbol Pin Definitions and Functions BGA BALL In/ Out1) Functions External Bus Unit Interface external address/data bus (multiplexed bus mode) or data bus (demultiplexed bus mode) for the EBU: AD0 Address/data bus / Data bus line 0 AD1 Address/data bus / Data bus line 1 AD2 Address/data bus / Data bus line 2 AD3 Address/data bus / Data bus line 3 AD4 Address/data bus / Data bus line 4 AD5 Address/data bus / Data bus line 5 AD6 Address/data bus / Data bus line 6 AD7 Address/data bus / Data bus line 7 AD8 Address/data bus / Data bus line 8 AD9 Address/data bus / Data bus line 9 AD10 Address/data bus / Data bus line 10 AD11 Address/data bus / Data bus line 11 AD12 Address/data bus / Data bus line 12 AD13 Address/data bus / Data bus line 13 AD14 Address/data bus / Data bus line 14 AD15 Address/data bus / Data bus line 15 AD16 Address/data bus / Data bus line 16 AD17 Address/data bus / Data bus line 17 AD18 Address/data bus / Data bus line 18 AD19 Address/data bus / Data bus line 19 AD20 Address/data bus / Data bus line 20 AD21 Address/data bus / Data bus line 21 AD22 Address/data bus / Data bus line 22 AD23 Address/data bus / Data bus line 23 AD24 Address/data bus / Data bus line 24 AD25 Address/data bus / Data bus line 25 AD26 Address/data bus / Data bus line 26 AD27 Address/data bus / Data bus line 27 AD28 Address/data bus / Data bus line 28 AD29 Address/data bus / Data bus line 29 AD30 Address/data bus / Data bus line 30 AD31 Address/data bus / Data bus line 31
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
H4 J2 H1 H3 H2 G1 G4 F1 E1 D1 G3 G2 F4 C1 F3 F2 E3 B1 E2 E4 A1 D2 D3 C2 C3 B2 A2 B3 A3 A4 B4 C4
I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s
Data Sheet
5
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol Pin Definitions and Functions BGA BALL In/ Out1) Functions External Bus Unit Interface (continued) external address bus for the EBU or chip select output lines. A0 Address bus line 0 A1 Address bus line 1 A2 Address bus line 2 A3 Address bus line 3 A4 Address bus line 4 A5 Address bus line 5 A6 Address bus line 6 A7 Address bus line 7 A8 Address bus line 8 A9 Address bus line 9 A10 Address bus line 10 A11 Address bus line 11 A12 Address bus line 12 A13 Address bus line 13 A14 Address bus line 14 A15 Address bus line 15 A16 Address bus line 16 A17 Address bus line 17 A18 Address bus line 18 A19 Address bus line 19 A20 Address bus line 20 A21 Address bus line 21 A22 Address bus line 22 A23 Address bus line 23 CS0 Chip select output 0 CS1 Chip select output 1 CS2 Chip select output 2 CS3 Chip select output 3 CS4 Chip select output 4 CS5 Chip select output 5 CS6 Chip select output 6 CSEMU Chip select for emulator region CSOVL Chip select for emulator overlay memory
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CSEMU CSOVL
R3 P4 T1 R2 R1 P3 P2 P1 N3 N2 N1 M4 M3 L4 M2 M1 L3 L1 L2 K4 K3 J4 K2 J3 R7 N7 P7 T6 R6 T5 P6 R8 T8
I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s O,u O,u O,u O,u O,u O,u O,u O,u O,u
Data Sheet
6
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol Pin Definitions and Functions BGA BALL In/ Out1) Functions External Bus Unit Interface (continued) control bus for the EBU control lines. RD Read control line RD/WR Write control line ALE Address latch enable ADV Address valid output Byte control line 0 BC0 BC1 Byte control line 1 BC2 Byte control line 2 BC3 Byte control line 3 Wait input WAIT BAA Burst address advance output EBUCLK External Bus Clock BFCLK0 Additional clock CSGLB Chip Select Global CMDELAY Command Delay MR/W Motorola-style Read/Write CKE Clock Enable RAS Row Address Strobe CAS Column Address Strobe Port 0 Port 0 is an 8-bit general purpose I/O port, overlaid with codec digital signals and external interrupt inputs (P0.[3:0]). M14 M15 M16 L14 L15 K13 L16 K14 I/O I/O I/O I/O I/O I/O I/O I/O EXI0IN EXI1IN EXI2IN EXI3IN SCLK LRCK MUTE0 MUTE1 External Interrupt Input 0 External Interrupt Input 1 or DATA_IN External Interrupt Input 2 or DATA_OUT External Interrupt Input 3 or MCLK
RD RD/WR ALE ADV BC0 BC1 BC2 BC3 WAIT BAA EBUCLK BFCLK0 CSGLB CMDELAY MR/W CKE RAS CAS P0
R4 P5 R10 N9 N6 R5 T4 T3 T7 P8 J1 K1 N8 T9 R9 P9 N5 T2
I/O,u I/O,u O,d O,u I/O,u I/O,u I/O,u I/O,u I/O,u O,u O,u O,u O,u I,u O,u O,u O,u O,u
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
Data Sheet
7
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol P1 Pin Definitions and Functions BGA BALL In/ Out1) Functions Port 1 Port 1 is a 8-bit bidirectional General Purpose I/O port P14 R16 P15 P16 N14 N15 N16 M13 I/O I/O I/O I/O I/O I/O I/O I/O GPIO only GPIO only GPIO only GPIO only GPIO only GPIO only GPIO only GPIO only Port 2 Port 2 is a 16-bit bidirectional general purpose I/O port and input/output for serial interfaces (IIC, ASC0, SSC) A16 G13 G14 A15 F15 B15 E15 C15 F13 F14 D15 E14 D14 E13 C14 B14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO only GPIO only GPIO only GPIO only GPIO only GPIO only SCL IIC Serial Port Clock SDA IIC Serial Port Data Open Drain GPIO Open Drain GPIO RXD0 ASC0 receiver input/output TXD0 ASC0 transmitter output SCLK SSC clock line MRST SSC Master Receive / Slave Transmit MTSR SSC Master Transmit / Slave Receive GPIO/EXI4IN/PLL_CLC.LOCK Monitoring of the PLL_CLC.LOCK
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15
Data Sheet
8
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol P3 Pin Definitions and Functions BGA BALL In/ Out1) Functions Port 3 Port 3 is a 16-bit bidirectional general purpose I/O port which is also used as input/output for serial interfaces (ASC1) and timer (GPTU) J13 K16 K15 J16 H13 H14 J15 H15 H16 D16 G16 E16 F16 G15 C16 B16 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPTU.0 GPTU I/O line 0 GPTU.1 GPTU I/O line 1 GPTU.2 GPTU I/O line 2 GPTU.3 GPTU I/O line 3 GPTU.4 GPTU I/O line 4 GPTU.5 GPTU I/O line 5 GPTU.6 GPTU I/O line 6 GPTU.7 GPTU I/O line 7 RXD1 ASC1 receiver input/output TXD1 ASC1 transmitter output GPIO only GPIO only / OSCBYP Latch-In Input Pin EXI5IN/ HWCFG0 Latch-InExternal Interrupt Input 5 EXI6IN/ HWCFG1 Latch-InExternal Interrupt Input 6 EXI7IN/ HWCFG2 Latch-InExternal Interrupt Input 7 GPIO only CODEC D9 B9 C11 B12 C10 B10 B11 D11 D12 C12 I I O O I I O O I I CODEC 0 Non-Inverting Input CODEC 0 Inverting Input CODEC 0 Non-Inverting Output CODEC 0 Inverting Output CODEC 1 Non-Inverting Input CODEC 1 Inverting Input CODEC 1 Non-Inverting Output CODEC 1 Inverting Output Codec External Clock Input Codec Disable (power saving)
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 CODEC AI0+ AI0AO0+ AO0AI1+ AI1AO1+ AO1CEXT CODEC_DIS
Data Sheet
9
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol DEBUG TRST TCK TDI TDO TMS OCDSE BRKIN BRKOUT Test SCAN_MODE PLLCTRL_AO TM_CTRL0 TM_CTRL1 Reserved Pins HS0 HS1 HS2 HS3 HS4 HS5 HS6 HS7 HS8 HS9 HS10 HS11 HS12 HS13 HS14 HS15 BYPASS NMI HRST N12 T13 R12 T12 J10 H10 P11 N11 R11 T11 P10 N10 T10 K9 K8 J7 A12 A13 B13 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I,d I,u I/O,u T16 R15 T15 R14 P13 T14 R13 P12 J14 D8 C7 C5 I,d I,u I,u O I,u I,u I,u O I I I I Pin Definitions and Functions BGA BALL In/ Out1) Functions DEBUG (OCDS/JTAG Control) Reset/module enable JTAG clock input Serial data input Serial data output State machine control signal OCDS enable input OCDS break input OCDS break output Test Pins Scan Mode Control current of different analog stages Test Mode Control 0 Test Mode Control 1 Reserved Internal Test and Heat Sink Pins. Must be routed as isolated pads on the PCB. Heat Sink 0 Heat Sink 1 Heat Sink 2 Heat Sink 3 Heat Sink 4 Heat Sink 5 Heat Sink 6 Heat Sink 7 Heat Sink 8 Heat Sink 9 Heat Sink 10 Heat Sink 11 Heat Sink 12 Heat Sink 13 Heat Sink 14 Heat Sink 15 PLL Bypass Control Input Non-Maskable Interrupt Input Bidirectional Hardware Reset
Data Sheet
10
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol PORST CLKOUT XTAL1 XTAL2 XTAL3 XTAL4 VAREF_COD VAGND_COD VDD_COD0/1 VSSA_COD0/1 VDD_GUARD VSS_GUARD VDD_OSCI VDD_RTC VSSA_32K VDDP_PLL VSSP_PLL VDDPLL VSSPLL VDDR VDDSB VDD_PWR Pin Definitions and Functions BGA BALL C13 A14 A6 A7 D5 C6 D10 C9 A10 A11 B8 C8 D7 A5 B5 B6 B7 A9 A8 D6 L13 D4 D13 H7 N4 N13 G7 G10 K7 K10 In/ Out1) I,u O I O I O Functions Power-on Reset Input (must be active during power up) CPU Clock Output PLL/Oscillator Input/Output Real Time Clock Oscillator input/output (32 KHz) Codec 0,1 Reference Voltage Codec 0,1 Reference Ground Codec Pad and Analog Power Supply (3.3V) Codec Pad and Analog Ground Guard Ring Supply (1.8V) Guard Ring Ground (1.8V) Main Oscilator Power Supply (1.8V) RTC Oscilator Core Supply (1.8V) RTC and Main Osc. Core Ground (1.8V) RTC and Main Osc. Supply (3.3V) RTC and Main Osc. Ground (3.3V) PLL Supply (1.8V) PLL Ground (1.8V) SRAM Power Supply (1.8V) SRAM Stand-By Power Supply (1.8V) 3.3V Power Supply
VDD_PWR2
1.8V Power Supply
Data Sheet
11
V 1.0, 2003-10
TC1910
PRELIMINARY Table 0-1 Symbol VSS_GND Pin Definitions and Functions BGA BALL G8 G9 H8 H9 J8 J9 In/ Out1) Functions Digital Power Ground
1)
The notification ',u' after the input/output type defines an internal pull-up resistor. An internal pull-down resistor is indicated by ',d'. For the lines AD[31:0] and A[23:0], the type of the pull device can be selected 's'.
Data Sheet
12
V 1.0, 2003-10
TC1910
PRELIMINARY System Architecture and Control 32-Bit TriCore CPU * * * * * * * * * * 32-bit architecture with 4-GByte unified data, program and input/output address space Fast automatic context-switch Dual 16 x 16 Multiply-accumulate (MAC) unit Saturating integer arithmetic Register based design with multiple variable register banks Bit handling Packed data operations Zero overhead loop Precise exceptions Flexible power management
Instruction Set with High Efficiency: * 16/32-bit instructions for reduced code size * Little endian byte ordering with support for big and little endian byte ordering at bus interface * Boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double word integers and IEEE-754 single precision floating-point data types * Bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats * Powerful instruction set * Flexible and efficient addressing mode for high code density
Data Sheet
13
V 1.0, 2003-10
TC1910
PRELIMINARY On-chip Code Memories Local Memory Bus Memory (LMBRAM): Address range of the 64 KByte Local Memory Bus Memory: * C000 0000H - C000 FFFFH (in segment 12 for cached operation) * E800 0000H - E800 FFFFH (in segment 14 for non-cached operation) PMU Scratch-Pad SRAM (CSRAM): The Program Memory Unit (PMU) memory consists of 24-KByte Code Scratchpad RAM (CSRAM) and 8-KByte Instruction Cache (ICACHE). Address range of the CSRAM: * D400 0000H - D400 5FFFH On-chip Data Memories DMU Scratch-Pad SRAM (DSRAM): The Data Memory Unit (DMU) memory consists of 24-KByte Data Scratchpad RAM (DSRAM) and 8-KByte Data Cache (DCACHE). Address range of the DSRAM: * D000 0000H - D000 5FFFH FPI-Bus Data Memory (FPIDRAM): The FPI-Bus Data Memory (FPIDRAM) is a 16-KByte static RAM located on the FPIBus. It contains two parts: FPIDRAM0 and FPIDRAM1. One half of it (FPIDRAM1) can be used for standby power operation. Address range of the FPI Data Memory: * 9FFF 8000H - 9FFF BFFFH (in segment 9 for cached operation) * BFFF 8000H - BFFF BFFFH (in segment 11 for non-cached operation)
Data Sheet
14
V 1.0, 2003-10
TC1910
PRELIMINARY System Control Unit (SCU) The System Control Unit of the TC1910 basically handles all system control tasks. All these system functions are tightly coupled and therefore they are handled physically by one unit, the SCU. The system tasks of the SCU are: * * * * * * * Clock Generation and Control Reset control Power Management control and wake-up Watchdog timer Device identification Standby SRAM control External interrupt capability (8 sources)
System timer (STM) The System Timer is designed for global system timing applications requiring both high precision and long range. It is used by the CPU for software operating system issues. Features: * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock, f STM (normally identical with the system clock). Counting begins at power-on reset Continuous operation is not affected by any reset condition except power-on reset
External Bus Interface (EBU_LMB) EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1910 and also to the FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus. Any LMB masters thus can access external memories or devices through EBU_LMB. Currently the maximum length of the bursts are according to the size of program and data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8bit, 16-bit and 32-bit wide access.
Data Sheet
15
V 1.0, 2003-10
TC1910
PRELIMINARY
E B U _L M B External Bus 32-bit L M B B us 64 -bit XBC B uffer S lo w e r D evices 50 M H z
SDRAM
DME F P I B us 32 -bit XM I
E xterna l M aster
E B U L 30 4 5 _L
E xte rn al B us U nit
Figure 4
EBU_LMB block diagram
Features supported in EBU_LMB: * * * * * * * * * * * * * * * * * * Local Memory Bus (LMB 64-bit) support. External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4. Highly programmable access parameters. Intel-style and Motorola-style peripheral/device support. SDRAM support (burst access, multibanking, precharge, refresh). 16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices. Burst flash support. Multiplexed access (address & data on the same bus) when DRAM is not present on the External Bus. Data Buffering: Code Prefetch Buffer, Read/Write Buffer. External master arbitration (compatible to C166 and other TriCore devices). 8 programmable address regions (1 dedicated for emulator). Little-Endian and Big-Endian support. CSglb signal, dedicated pin, bit programmable to combine one or more CS lines, for buffer control. RMW signal reflecting a read-modify-write action. Signal for controlling data flow of slow-memory buffer. Slave unit for external (off-chip) master to access devices on the FPI bus. Master unit for FPI master to access external (off-chip) devices. Data Mover Engine.
Data Sheet
16
V 1.0, 2003-10
TC1910
PRELIMINARY Interrupt System * Flexible interrupt prioritizing scheme with 256 interrupt priority levels * Fast interrupt response
M o d u le A M o d u le K e rn e l n S e rvice R e q u e st Nodes
C P U In te rru p t A rb itra tio n B u s
M a in In te rru p t C o n tro l CPU In te rru p t C o n tro l U n it (IC U )
M o d u le B M o d u le K e rn e l n S e rvice R e q u e st Nodes
CPU C o re 4
4 S e rvice R e q u e st Nodes M o d u le C M o d u le K e rn e l n S e rvice R e q u e st Nodes
Figure 5
Block Diagram Interrupt System
Data Sheet
17
V 1.0, 2003-10
TC1910
PRELIMINARY FPI-Bus The Flexible Peripheral Interconnect Bus is designed with the requirements of highperformance Systems-on-Chip in mind. Key Features: * * * * * * * * * * Core independent Multi-master capability Demultiplexed operation Clock synchronous Peak transfer rate of up to 200 MBytes/s (@ 50 MHz bus clock) Address and data bus scalable (32 bit address bus, 32 bit data bus ) 8-/16- and 32 bit data transfers Broad range of transfer types from single to multiple data transfers Burst transfer capability EMI and power consumption minimized
LMB-Bus The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. All signals relate to the positive clock edge. The protocol supports 8,16,32 & 64 bits single beat transactions and variable length 64 bits block transfers. Key Features: The LMB provides the following features: * * * * * * * Optimized for high speed and high performance 32 bit address, 64 bit data busses Central simple per cycle arbitration Slave controlled wait state insertion Address pipelining (max depth - 2) Split transactions Variable block length - 2, 4 or 8 beats of 64 bit data
Data Sheet
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TC1910
PRELIMINARY On-Chip Debug System (OCDS) The TC1910 architecture is supporting OCDS Level 1. This means access to FPI Bus and the whole FPI address space via the JTAG interface pins. On-Chip Peripheral Units The TC1910 offers several on-chip peripheral units such as serial controllers, timer units, and Codec module. Within the TC1910 all these peripheral units are connected to the TriCore CPU/system via the FPI (Flexible Peripheral Interconnect) Bus. Several IO lines on the TC1910 ports are reserved for these peripheral units to communicate with the external world. Peripheral Units of the TC1910: * Three Asynchronous/Synchronous Serial Channels with baudrate generator, parity, framing and overrun error detection, IrDA mode, FIFO buffers. * One High Speed Synchronous Serial Channels with programmable data length and shift direction * IIC module * One multi-functional General Purpose Timer Units with three 32-bit timer/counter * Dual channel Codec interface * GPIO blocks Table 1 Module Asynchronous Serial Channel 0 (ASC0) Asynchronous Serial Channel 1 (ASC1) Peripheral Modules Address Range F000 0A00H F000 0AFFH I/O Lines RDX0, TDX0 Interrupt Nodes ASC0_TSRC ASC0_RSRC ASC0_ESRC ASC0_TBSRC ASC1_TSRC ASC1_RSRC ASC1_ESRC ASC1_TBSRC SSC_TSRC SSC_RSRC SSC_ESRC IIC_XP0SRC IIC_XP1SRC IIC_XP2SRC RTC_SRC
F000 0B00H F000 0BFFH
RDX1, TDX1
Synchronous Serial F000 0800H Channel (SSC) F000 08FFH Inter-IC Bus (IIC) F000 0500H F000 05FFH F000 0100H F000 01FFH
SCLK, MRST, MTSR SCL, SDA -
Real Time Clock (RTC)
Data Sheet
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TC1910
PRELIMINARY Table 1 Module System Timer Unit (STM) General Purpose Timer (GPTU) Speech Interface (Codec) Peripheral Modules (cont'd) Address Range F000 0300H F000 03FFH F000 0700H F000 07FFH F000 2400H F000 24FFH I/O Lines GPTU 2*2 analog IN, 2*2 analog OUT, CEXT, CODEC_DIS Interrupt Nodes GPTU_SRC0..7 CODEC_SRC0..5
Data Sheet
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TC1910
PRELIMINARY Asynchronous/Synchronous Serial Interfaces (ASC 0/1) The Asynchronous/Synchronous Serial Interface ASC provides serial communication between the TriCore and other microcontrollers, microprocessors or external peripherals. Features: * Full duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baudrate from 3.125 MBaud to 0.74 Baud (@ 50 MHz module clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability * Half-duplex 8-bit synchronous operating mode - Baudrate from 6.25 MBaud to 637 Baud (@ 50 MHz module clock) * Double buffered transmitter/receiver * Interrupt generation - on a transmitter buffer empty condition - on a transmit last bit of a frame condition - on a receiver buffer full condition - on an error condition (frame, parity, overrun error) * Support for IrDA * Automatic Baudrate Detection * 8 Byte FIFO
C lo c k C on tro l
f hw _c lk
A d d re s s D e c od e r T IR T B IR R IR E IR A B S TIR A B D E T IR
RXD ASC M od u le (K e rn e l) TX D P o rt C o n tro l
RXD TX D
Interru p t C on tro l
M C A 05 2 53
Figure 6
General Block Diagram of the ASC Interface
Data Sheet
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TC1910
PRELIMINARY High-Speed Synchronous Serial Interface (SSC) The High Speed Synchronous Serial Interface SSC provides serial communication between microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication up to 25 MBaud (@ 50 MHz module clock). The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits : 2 to 16 bit - Programmable shift direction : LSB or MSB shift first - Programmable clock polarity : idle low or high state for the shift clock - Programmable clock/data phase : data shift with leading or trailing edge of SCLK * Maximum baudrate: 25 MBaud in Master, 12.5 in Slave mode (@ 50 MHz module clock) Interrupt generation - on a transmitter empty condition - on a receiver full condition - on an error condition (receive, phase, baudrate, transmit error) * Three pin interface
C lo c k C on tro l
f h w _c lk
Slave Master RXD TXD RXD TXD S la v e M a s te r SCLK P o rt C o n tro l M TSR
A d d re s s D e c o de r E IR Interru p t C on tro l R IR T IR
SSC M o d ule (K erne l)
M RST
SCLK
M C B 04 5 0 5_ m o d
Figure 7
General Block Diagram of the SSC Interface
Data Sheet
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TC1910
PRELIMINARY Inter-IC Interface (IIC) IIC supports a certain protocol to allow devices to communicate directly with each other via two wires. One line is responsible for clock transfer and synchronization (SCL), the other is responsible for the data transfer (SDA). The on-chip IIC Bus module connects the platform buses to other external controllers and/or peripherals via the two-line serial IIC interface. The IIC Bus module provides communication at data rates of up to 400 kBit/s and features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to the IIC bus protocol. The module can operate in three different modes: Master mode, where the IIC controls the bus transactions and provides the clock signal. Slave mode, where an external master controls the bus transactions and provides the clock signal. Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can be master or slave. The on-chip IIC bus module allows efficient communication via the common IIC bus. The module unloads the CPU of low level tasks like: * * * * * * * * * * (De)Serialization of bus data. Generation of start and stop conditions. Monitoring the bus lines in slave mode. Evaluation of the device address in slave mode. Bus access arbitration in multimaster mode. Extended buffer allows up to 4 send/receive data bytes to be stored. Selectable baud rate generation. Support of standard 100 kBaud and extended 400 kBaud data rates. Operation in 7-bit addressing mode or 10-bit addressing mode. Flexible control via interrupt service routines or by polling.
IIC Features:
Data Sheet
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TC1910
PRELIMINARY Timer Unit (GPTU) Figure 8 shows a global view of all functional blocks of the GPTU module.
C lo c k C on tro l
fG P T U
A d d re s s D e c od e r SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 G PTU M od u le (K e rn e l)
IN 0 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 P o rt C o ntro l
IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7
P 0.0 / G P T 0 P 0.1 / G P T 1 P 0.2 / G P T 2 P 0.3 / G P T 3 P 0.4 / G P T 4 P 0.5 / G P T 5 P 0.6 / G P T 6 P 0 .7 / G P T 7
M C B 0 5 0 52 _ m o d ifie d
Interru p t C on tro l
Figure 8
General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight inputs and eight outputs. The three timers of the GPTU module T0, T1, and T2, can operate independently from each other, or can be combined: General Features: * * * * All timers are 32-bit precision timers with a maximum input frequency of fGPTU/2. Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer
Features of T0 and T1: * Each timer has a dedicated 32-bit reload register with automatic reload on overflow * Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers * Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events * Two input pins can determine a count option
Data Sheet
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TC1910
PRELIMINARY Features of T2: * Optionally count up or down * Operating modes: - Timer - Counter - Incremental Interface Mode * Options: - External start/stop, one-shot operation, timer clear on external event - Count direction control through software or an external event - Two 32-bit reload/capture registers * Reload modes: - Reload on overflow or underflow - Reload on external event: positive transition, negative transition, or both transitions * Capture modes: - Capture on external event: positive transition, negative transition, or both transitions - Capture and clear timer on external event: positive transition, negative transition, or both transitions * Can be split into two 16-bit counter/timers * Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. * Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins * T2 events are freely assignable to the service request nodes. Real Time Clock Unit RTC The Real Time Clock (RTC) module is basically an independent timer chain and counts clock ticks. The base frequency of the RTC can be programmed via a reload counter. The RTC can work fully asynchronous to the system frequency and is optimized on low power consumption. Features: The RTC serves different purposes: * * * * Absolute system clock to determine the current time and date Cyclic time based interrupt Alarm interrupt for wake up on a defined time 48-bit timer for long term measurements
Data Sheet
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TC1910
PRELIMINARY Codec Interface The speech A/D and D/A converters (called codec) is designed for telephone and speech recognition quality. They can be used for microphone / earpiece applications. The TC1910 configuration implements a dual channel speech codec connected to the FPI bus.
VDD
C O D0
VSS
COD0
V DD V SS
CO D 1 CO D 1
ch0 n on -inv. inpu t C lock C on trol
f pe r
A I0 + A I0 A O 0+ A O 0A I1 + A I1 A O 1+ A O 1C O D E C _ D IS CEXT M UTE0 M UTE1 IIS sig na ls
ch0 in v. inp ut ch0 n on -inv. outp ut ch0 in v. ou tp ut
A d dre ss D e co de r SR0 SR1 SR2 SR3 SR4 SR5 CO DEC M o dule K e rn el
ch1 n on -inv. inpu t ch1 in v. inp ut ch1 n on -inv. outp ut ch1 in v. ou tp ut clock disab le external clock inp ut m ute ch ann el 0 m ute ch ann el 1
In terrup t C on trol
V RE F
COD
VGND
COD
5
C od ec b ypass
Figure 9
General Codec Overview
General Purpose I/Os (GPIO) * * * * Push/pull output drivers 3.3 Volt operation for GPIO Programmable pull-up/-down devices at all pins Optional Open Drain Output Mode
Data Sheet
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TC1910
PRELIMINARY ID Register Table Table 2 SCU_ID MANID CHIPID RTID RTC_ID BCU_ID STM_ID JDP_ID IIC_ID GPTU_ID SSC_ID ASC0_ID ASC1_ID CODEC_ID CPS_ID CPU_ID EBU_ID DMU_ID PMU_ID LCU_ID LFI_ID List of TC1910 ID registers Address F000 0008H F000 0070H F000 0074H F000 0108H F000 0208H F000 0308H F000 0408H F000 0508H F000 0708H F000 0808H F000 0A08H F000 0B08H F000 2408H F7E0 FF08H F7E1 FE18H F800 0008H F87F FC08H F87F FD08H F87F FE08H F87F FF08H Reset Value 0019 C002H 0000 1820H 0000 8902H 0000 0000H 0000 5A04H 0000 6A06H 0000 C002H 0000 6305H 0000 4604H 0001 C002H 0000 4503H 0000 44E1H 0000 44E1H 001C C002H 0015 C004H 000A C003H 0014 C003H 0008 C002H 000B C002H 000F C003H 000C C003H SCU Identification Register Manufacturer Identification Register Chip Identification Register RTC Module Identification Register BCU Identification Register System Timer Module Identification Register JTAG/OCDS Module Identification Register IIC Module Identification Register GPTU Module Identification Register SSC Module Identification Register ASC Module Identification Register ASC Module Identification Register Codec Identification Register CPU Module Identification Register CPU Identification Register EBU_LMB Module Identification Register DMU Identification Register PMU Module Identification Register LCU Identification Register LFI Identification Register Short Name Description
Redesign Tracing Identification Register F000 0078H
Data Sheet
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TC1910
PRELIMINARY Power Supply Figure 10 shows the TC1910 power supply concept, where certain logic modules are individually supplied with power. In this way, the noise margin is improved in the especially sensitive modules, like the A/D converter and the CODEC.
V D DA V SSA V D DA V SS A V DD A V SSA V DD A V SSA V D DA V SS A V DD A V SSA
M A IN OSC
RTC OSC
PLL (ana log)
ADC (ana log)
CO DEC 0 (a na lo g)
CODEC 1 (ana log)
V D DP V SS P X V D DP V SS P Y V D D_SB V D DR V SS V DD V SS VDD V SS B atte ry B acked S ta nd- B y S RAM A LL D IG IT A L C O R E CO MPO NENTS
Figure 10
TC1910 Power Supply Concept
Data Sheet
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TC1910
PRELIMINARY Power-Up Sequence During Power-Up reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-Up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the core VDD power supply reaches its operating value first, and then the GPIO VDDP power supply. During the rising time of the core voltage it must be ensured that 0< VDD-VDDP <0.5 V. During power-down, the core and GPIO power supplies VDD and VDDP respectively, have to be switched off until all capacitances are discharged to zero, before the next power-up.
Note: The states of the pins are undefined when only the port voltage VDDP is on.
Data Sheet
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TC1910
PRELIMINARY Electrical characteristics
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the TC1910 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the TC1910 will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the TC1910.
Data Sheet
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TC1910
PRELIMINARY Absolute Maximum Ratings Parameter Ambient temperature Symbol -40 -65 - -0.5 -0.3 -0.3 -0.3 -0.5 -10 - - Limit Values min. max. 85 150 125 4.2 2.1 2.1 2.1 4.2 10 |100| 1.0 C C C V V V V V mA mA W PLL under bias under bias Unit Notes
TA TST Storage temperature Junction temperature TJ Voltage on I/O Supply pins with VDDP
respect to ground (VSS) Voltage on Core Supply pins with respect to ground (VSS) Voltage on PLL Supply pins with respect to ground (VSS)
VDD VDDPLL
Voltage between Oscillator VDDOSC Supply Pins and ground (VSS). Voltage on any pin with respect VIN to ground (VSS) Input current on any pin during IOV overload condition Absolute sum of all input currents at overload condition Power dissipation IOV
PDISS
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN>VDD or VINData Sheet
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TC1910
PRELIMINARY Package Parameters (P-LBGA-208) Parameter Power dissipation Thermal resistance Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1910. All parameters specified in the following sections refer to these operating conditions, unless otherwise noted. Parameter Supply voltage Symbol Limit Values min. max. 3.61) 1.892) 1.89 1.89 0 -5 5 V V V V V mA I/O supply Core supply PLL supply Oscillator supply 3.0 1.71 1.71 1.71 Unit Notes Symbol Limit Values min. max. 1.0 30 W - K/W Chip to ambient - - Unit Notes
PDISS RTHA
Ground voltage Input current on any pin during overload condition
VDDP VDD VDDPLL VDDOSC VSS
IOV
VOV > VDDP + 0.3V VOV < VSS - 0.3V
Absolute sum of all input | IOV| currents at overload condition Ambient temperature under bias CPU clock External Load Capacitance
1)
-
|50|
mA
TA fCPU CL
-40 - -
85 66 50
C MHz pF
Voltage overshoot to 4 V is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h Voltage overshoot to 2 V is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h
2)
Data Sheet
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TC1910
PRELIMINARY DC Characteristics GPIO pins Parameter Output low voltage (strong driver) Output high voltage (strong driver) Output low voltage (medium driver)1) Output high voltage (medium driver)1) Output low voltage (weak driver)1) Output high voltage (weak driver)1) Input low voltage Input high voltage Symbol VOL VOH VOL VOH VOL VOH VIL VIH Limit values min. 2.4 2.4 2.4 -0.3 2.0 max. 1 0.4 0.4 0.4 0.8 V V V V V V V Unit Test Conditions IOL = 10 mA IOL = 2.5 mA IOH = - 2.5 mA IOL = 1 mA IOH = - 1 mA IOL = 100 A IOH = - 100 A LVTTL whatever is lower 0V< Vin < VDDP VOUT = 2.0V VOUT = 0.8V VOUT = 0.8V VOUT = 2.0V f = 1MHz @ TA = 25oC
VDDP+0.3 V or 3.7V 500 1 0.8 10 nA A A A A pF
Input leakage current Pull-up current 2) Pull-up current
3)
IOZ1 |IPUH | |IPUL| |IPDL| |IPDH| CIO
20 20 -
Pull-down current Pull-down current Pin capacitance1)
1) 2) 3)
Not subject to production test, verified by design/characterization. The maximum current that may be drawn while the respective signal line remains inactive. The minimum current that must be drawn in order to drive the respective signal line active.
Data Sheet
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TC1910
PRELIMINARY NMI Pin NMI Pin is an input pin with different Pull-Up characteristics than other pins. The related characteristics are given in the following table Parameter Symbol Limit values min. Max. current allowed |IPUH | through the Pull-Up device while pin (input) voltage remains still at the high level Min. current needed |IPUL | through the Pull-Up device so that pin voltage is driven to the low level. max. 4 uA Unit Test Conditions VOUT=2.0V
100
-
uA
VOUT=0.8V
Note: NMI Pin does not have a Pull-Down device.
Oscillator Pins
Parameter Input leakage current (analog input) at XTAL11) Input low voltage XTAL1 Input high voltage XTAL12)
Symbol IOZ1 CC VILX SR VIHX SR
Limit values min. max. 200
Unit nA
Test Conditions 0V< Vin < VDDP
0.8
0.3 VDD-0.3 VDD-0.35 VDD-0.4 VDD-0.43 20 0.5
V V
fOSC=4MHz fOSC=8MHz fOSC=12MHz fOSC=16MHz 0V < VIN < VDD 0V < VIN < VDD
XTAL1 input current XTAL3 input current2)
1) 2)
IIX1 CC IIX3 CC
-
A A
Only applicable in deep sleep mode Not subject to production test, verified by design/characterization.
Data Sheet
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TC1910
PRELIMINARY IIC Pins Each IIC Pin is an open drain output pin with different characteristics than other pins. The related characteristics are given in the following table Parameter Output low voltage Input high voltage1) Input low voltage1) Input leakage current Pin capacitance1)
1)
Symbol VOL CC VIH SR VIL SR IOZ2 CC CIO CC
Limit values min. 0.7VDDP -0.3 max. 0.4 0.6 3.6 0.3VDDP + - 500 10
Unit V V V nA pF
Test Conditions 3 mA 6 mA -
f=1MHz@ TA=25oC
Not subject to production test, verified by design/characterization.
Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.60 V must be applied to these pads. Note: IIC pins have no Pull-Up and Pull-Down devices.
Data Sheet
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TC1910
PRELIMINARY Codec Electrical Characteristics
Parameter Digital supply voltage Analog supply voltage Analog supply ground Analog reference ground Analog input voltage (RMS) Analog output voltage (RMS) Input Resistace of the Analog Inputs4)
Symbol VDD VDDA VSSA VAGND VAIN VAOUT Rain
Limit values min. 1.71 3.0 -0.1 1.14 typ. 1.8 3.3 0.0 1.2 max. 1.89 3.6 +0.1 VSSA+ 0.05 0.775 0.775 30 -
Unit V V V V Vrms Vrms
Test Conditions
External reference voltage VAREF1)
+1.262) V
VSSA- VSSA 0.05
3)
kOhm differential input, gain: -12,-6, 0 dB kOhm single-ended input, gain: -12,-6, 0 dB kOhm differential input, gain: 6 to 30 dB kOhm single-ended input, gain: 6 to 30 dB V AGCCR. BGPSEL[1,0] =00
-
15
-
-
60
-
-
30
-
Internal Reference Voltage Vref (Bandgap Voltage)5)
1)
VBGP
1.1
1.2
1.3
Reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping margins, increased/decreased gain. VSSA=VAGND=0V Please take the gain settings of the analog preamplifier into account, therefore Vimaxreal=Vimax/gain Simulation value. For external usage, Bandgap reference voltage is strongly dependent on the external load (<500 MOhm). In this case, high impedance buffer must be used.
2) 3) 4) 5)
Data Sheet
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TC1910
PRELIMINARY Codec ADC and DAC path characteristics
Parameters Attenuation distortion (ref. freq. 1014 Hz) (ref. level 0dBm0)2)
min.
typ.
max.
Unit dB dB dB dB dB
Test conditions1)
0 -0.25 -0.25 -0.25 0 -55 -0.3 -0.6 -1.6 -80 -80 -60 -0.8 0
0.25 0.45
< 0.025 0.025-0.0375 0.0375-0.3 0.3-0.425 > 0.425 at 0dBm0 +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 receive &transmit
Signal to total distortion Gain tracking (ref. freq. 1014 Hz) (ref. level 0dBm0)2) Idle channel noise
-45 0.3 0.6 1.6 -75 -75 -50 0.8
dB dB dB dB dBm 0 dB dB dB
Cross talk Harmonic distortion Gain (ref. freq. 1014 Hz) (ref. level 0dBm0)2) Power supply rejection ratio (PSRR)
1)
at 0dBm0 receive &transmit
-
-60 -40
-35 -35
dB dB
Receive (0.0375-0.425)3) Transmit(0.0375-0.425)3)
Values given in this table are valid for all sampling frequencies.
2)
3)
0dBm0 is equivalent to -12dBm is equal to 194.7 mVRMS.
Supply ripple 70 mV.
Note: Numbers without units in the test conditions column are relative frequency values to the chosen sampling frequency. e.g. 0.425 equals 3.4 kHz @ 8 kHz sampling frequency.
Data Sheet
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TC1910
PRELIMINARY Power Supply Current
Parameter Active mode supply current Idle mode supply current Deep sleep mode supply current
1)
Symbol
Limit values typ.
1)
Unit mA mA mA
Test Conditions Sum of all IDD. at 1.8V Core Supply at 1.8V Core Supply
max. - - -
IDD IID IDS
180 90 0.25
Typical values are measured at 25C, CPU clock at 66 MHz and nominal supply voltage, i.e. 3.3V for VDDP and 1.8V for VDD, VDDPLL, VDDOSC
Note: The Power Supply Current values refer to the total current at 1.8V power supply, at LMB/FPI bus frequency ratio of 2:1, while running an average application. These numbers are estimation based on average device measurements.
Data Sheet
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TC1910
PRELIMINARY AC Characteristics Operating Conditions apply. Output Rise/Fall Times GPIO pins Rise/fall time measurements are made between 10% and 90%. The following table is valid for the GPIO pins pad drivers. Output pad characteristics are controllable via DRVCTRx registers.
Pad Modus rise / fall time Strong driver * sharp edge * medium edge1) * soft edge1)
1)
Symbol
Limit values min. max. 3 6 12
Temp Unit Comp yes yes yes ns ns ns
Test Conditions @50pF @50pF @50pF
SF SM SS
-
Not subject to production test, verified by design/characterization.
Data Sheet
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TC1910
PRELIMINARY Timing Characteristics (Operating Conditions apply)
Note: Timing parameters are not subject to production test, they are verified by design/ characterization.
2 .4 V
2 .0 V
T e st P oin ts
2 .0 V 0 .8 V
M C T 0 4 88 0
0 .4 V
0 .8 V
AC inputs during testing are driven at 2.4V for a logic "1" and 0.4V for a logic "0". Timing measurements are made at VIHmin for a logic "1" and VILmax for a logic "0".
Figure 11
Input/Output Waveforms for AC Tests - for GPIO, Dedicated and EBU pins
Data Sheet
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TC1910
PRELIMINARY External Oscillator at XTAL1 Timing Requirements (Operating Conditions apply) Parameter Main Oscillator XTAL frequency1) Frequency of an external oscillator driving at XTAL12) Input Clock high time Input Clock low time Input Clock rise time Input Clock fall time
1) 2)
Symbol with/without PLL with PLL3) without PLL4)
Limits min. max. 16 25 25 - - 7 7 4 4 -
Unit MHz MHz ns ns ns ns
fOSC SR fOSCDD
SR
t1 t2 t3 t4
SR 16 SR 16 SR - SR -
Oscillator Bypass Pin P3.11 latch-in value high. Internal oscillator provides the input clock signal. Oscillator Bypass Pin P3.11 latch-in value low. Internal oscillator disabled. External oscillator provides the input clock signal. Internal PLL provides the system clock. BYPASS pin latch-in value low. PLL prescaler value P=1. Internal PLL bypassed. BYPASS pin latch-in value high. External oscillator provides the system clock directly. When CODEC modules is active its frequency limitations must be taken into consideration. Otherwise, minimum frequency in this mode can go as low as zero.
3) 4)
tO SC
In p u t C lo c k at XTAL1 0 .5 V D D O S C
t1
t2
t4
t3
V IH X V IL X
M C T 04 8 8 2
Figure 12
External Clock at XTAL1 Requirements
Note: VDDOSC, VIHX and VIHL are defined in the Oscillator Pins DC Characteristics Chapter. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier.
Data Sheet
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TC1910
PRELIMINARY CPU Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter CLKOUT period CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time Symbol Limits min. max. - - - 3 3 ns ns ns ns ns Unit
tCLKOUT 15
CC
t1 t2 t3 t4
CC CC CC CC
6 6 - -
t C P U C LK
C LK OU T 0 .5 V D D
t1
t2
t4
t3
0 .9 V D D 0 .1 V D D
M C T 0 4 88 3
Figure 13
CLKOUT Timing
Data Sheet
42
V 1.0, 2003-10
TC1910
PRELIMINARY PLL Parameters Parameter Accumulated jitter VCO frequency range Symbol Limit Values1) min. max. - MHz MHz MHz MHz MHz MHz MHz MHz s 1502) 200
3)
Unit
DN fVCO
see Figure 14 100 150 200 250
2504) 3005) 802) 1303) 1804) 2305) 200
PLL base frequency
fPLLBASE
20 20 20 20
PLL lock-in time
1) 2) 3) 4) 5)
tL
-
Not subject to production test, verified by design/characterization. @ vcosel = '00' @ vcosel = '01' @ vcosel = '10' @ vcosel = '11'
Note: When TC1910 starts-up with the PLL not bypassed, first user instructions are executed with the frequency defined by the VCO free-running frequency (fPLLBASE) and by the reset value of the PLL_CLC register (the K-divider and VCOSEL bitfields). It is software responsibility to initialize its own appropriate values in the bitfields in this register, before giving the command for the VCO to lock to the input frequency. For more information, see the Users Manual, System Units, System Control Unit chapter.
Data Sheet
43
V 1.0, 2003-10
TC1910
PRELIMINARY
5.0 ns DN 4.0
TC191x_pll_jitter
3.0 fSYS = fSYS = fSYS = fSYS = fSYS = 66 MHz (K = 4) 60 MHz (K = 5) 50 MHz (K = 6) 40 MHz (K = 7) 33 MHz (K = 8)
2.0
1.0
0.0 0 5 10 15 20 25 30 P 35 DN = Max. jitter P = Number of consecutive fSYS periods K = K-divider of PLL
Figure 14
Approximated Maximum Accumulated PLL Jitter
The following two formulas define the (absolute) approximate maximum value of jitter DN in [ns] dependent on the K-factor, the system clock frequency fSYS in [MHz], and the number P of consecutive fSYS periods. for P < 0.25x fSYS
DN [ns] = [( + 0.9) x fSYS x K
735
P fSYS x 0.25
+ 0.5 ] [1]
for P > 0.25x fSYS
DN [ns] = [
735 + 1.4 ] fSYS x K
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a specific value of P. Beyond this value of P the maximum accumulated jitter remains at a constant value.
Data Sheet
44
V 1.0, 2003-10
TC1910
PRELIMINARY Timing for EBU_LMB Clock Outputs (Operating Conditions apply; CL = 50 pF) Parameter EBUCLK period EBUCLK high time EBUCLK low time EBUCLK rise time EBUCLK fall time BFCLK0 period BFCLK0 high time BFCLK0 low time BFCLK0 rise time BFCLK0 fall time Symbol Limits min. max. - - - 2.5 2.5 - - - 3.5 2.5 ns ns ns ns ns ns ns ns ns ns 15 6 6 - - 20 9 9 - - Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
CC CC CC CC CC CC CC CC CC CC
t 1 (t 6 )
EBU CLK/ BFC LK 0 0 .5 V D D 0 .9 V D D 0 .1 V D D
t 2 (t 7 )
t 3 (t 8 )
t 5 (t 1 0 )
t 4 (t 9 )
M C T 0 4 88 4
Figure 15
EBU_LMB Clock Output Timing
Data Sheet
45
V 1.0, 2003-10
TC1910
PRELIMINARY Timing for SDRAM Access Signals (Operating Conditions apply; CL = 50 pF) Parameter CKE high from EBUCLK CKE low from EBUCLK A(23:0) output valid from EBUCLK A(23:0) output hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK RAS low from EBUCLK RAS high from EBUCLK CAS low from EBUCLK CAS high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK Symbol Limits min. max. 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17
CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 SR 2.0
t18 SR 4.0
Data Sheet
46
V 1.0, 2003-10
TC1910
PRELIMINARY
Write Access: EBUCLK
t1
CKE A(23:0)
t3
Row
t4
Column
t5
CSx
t6 t8
RAS
t7
CAS
t10 t9
t12 t14
RD/WR
t11
BC(3:0)
t13
AD(31:0)
Data (0) Data (n-1)
t15
Read Access: EBUCLK
t16
t2
CKE A(23:0) Row
t3
Column
t4 t6
CSx RAS CAS RD/WR BC(3:0)
t9
t10
t13
t14 t17 t18
Data (n-1)
MCT05319
AD(31:0)
Data (0)
Figure 16
SDRAM Access Timing
Data Sheet
47
V 1.0, 2003-10
TC1910
PRELIMINARY Timing for Burst Flash Access Signals Operating Conditions apply; CL = 50 pF) Parameter A(23:0) output valid from BFCLK0 A(23:0) output hold from BFCLK0 CS(6:0) low from BFCLK0 ADV low from BFCLK0 ADV high from BFCLK0 BAA low from BFCLK0 BAA high from BFCLK0 RD low from BFCLK0 AD(31:0) input setup to BFCLK0 AD(31:0) input hold from BFCLK0 Symbol Limits min. max. 11.0 - 9.0 10.0 - 10.0 - 10.0 - - ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t5 t6 t7 t8 t9 t11 t12
CC - CC 0.0 CC - CC - CC 3.0 CC - CC 3.0 CC - SR 6.0 SR 3.0
Data Sheet
48
V 1.0, 2003-10
TC1910
PRELIMINARY
BFCLK0
t1
A[23:0]
Address Valid
t2 t6
t5
ADV
t3
CSx
t9
RD
t7
BAA
t8
t11 t12
D[31:0]
Valid Valid
Note: Between the end of the Address Phase (ADV goes high) and the beginning of the Command Phase (RD goes low) several cycles of Command Delay Phase can be inserted.
mct04889_mod_la
Figure 17
Burst Flash Access Timing (Instruction Read)
Data Sheet
49
V 1.0, 2003-10
TC1910
PRELIMINARY Timing for Demultiplexed Access Signals1) (Operating Conditions apply; CL = 50 pF) Parameter ALE low from EBUCLK ALE high from EBUCLK A(23:0) output valid from EBUCLK A(23:0) output hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK MR/W low from EBUCLK MR/W high from EBUCLK RMW low from EBUCLK RMW high from EBUCLK RD low from EBUCLK RD high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK CMDELAY input setup to EBUCLK CMDELAY hold from EBUCLK WAIT input setup to EBUCLK WAIT hold from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK Symbol Limits min. max. 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - - - - 8.0 - 8.0 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24
CC - CC 2.0 CC - CC 2.0 CC - CC 2.0 CC - CC 2.0 CC - CC 1.0 CC - CC 0.0 CC - CC 2.0 SR 4.0 SR 3.0 SR 4.0 SR 3.0 CC - CC 2.0 CC - CC 0.0 SR 4.0 SR 4.0
1)
It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
50
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2 t3
A(23:0) Address
t4
t5
CSx
t6
t7
MR/W
t14
RD/WR
t16 t15 t13
CMDELAY
t18 t17
WAIT
t20 t19 t19 t20
BC(3:0)
t21
AD(31:0) Data Out
t22
MCT05320
Figure 18
Demultiplexed Write Access
Data Sheet
51
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2 t3
A(23:0) Address
t4
t6
CSx
t5
MR/W
t8
RMW
t10
t9
RD
t12 t16 t15 t11
CMDELAY
t18 t17
WAIT
t19
BC(3:0)
t19
t20
t23
AD(31:0) Note: RMW signal is available only during Read-Modify-Write Access. Data
t24
MCT05321
Figure 19
Demultiplexed Read Access
Data Sheet
52
V 1.0, 2003-10
TC1910
PRELIMINARY Timing for Multiplexed Access Signals1) (Operating Conditions apply; CL = 50 pF) Parameter ALE high from EBUCLK ALE low from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK MR/W low from EBUCLK MR/W high from EBUCLK RMW low from EBUCLK RMW high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK RD low from EBUCLK RD high from EBUCLK CMDELAY input setup to EBUCLK CMDELAY hold from EBUCLK WAIT input setup to EBUCLK WAIT hold from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK Symbol Limits min. max. 8.0 - 8.0 - - - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - - - - - 8.0 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22
CC - CC 2.0 CC - CC 0.0 SR 4.0 SR 4.0 CC - CC 1.0 CC - CC 2.0 CC - CC 1.0 CC - CC 2.0 CC - CC 0.0 SR 4.0 SR 3.0 SR 4.0 SR 3.0 CC - CC 2.0
1)
It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
53
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2 t3
AD(31:0) Address Data
t4
t7
CSx
t4 t3
t8
t9
MR/W
t14
RD/WR
t18 t17 t13 t20 t19
CMDELAY
WAIT
t22 t21 t21 t22
BC(3:0)
MCT05322
Figure 20
Multiplexed Write Access
Data Sheet
54
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2 t3
AD(31:0) Address
t5 t6
Data
t4
CSx
t8
t7
MR/W
t10
RMW
t12
t11
RD
t16 t18 t17 t15
CMDELAY
t20 t19
WAIT
t21
BC(3:0)
t21
t22
Note: RMW signal is only available during Read-Modify-Write Access.
MCT05323
Figure 21
Multiplexed Read Access
Data Sheet
55
V 1.0, 2003-10
TC1910
PRELIMINARY Timing for External Bus Arbitration Signals (Operating Conditions apply; CL = 50 pF) Parameter HOLD input setup to EBUCLK HOLD input hold from EBUCLK HLDA low from EBUCLK HLDA high from EBUCLK HLDA input setup to EBUCLK HLDA input hold from EBUCLK BREQ low from EBUCLK BREQ high from EBUCLK Symbol Limits min. max. - - 10.0 9.0 - - 10.0 9.0 ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8
SR 6.0 SR 8.0 CC - CC - SR 8.0 SR 8.0 CC - CC -
Note: The signals HOLD, HLDA and BREQ are alternate function of the CS5, CS6 and CSOVL Pins.
Data Sheet
56
V 1.0, 2003-10
TC1910
PRELIMINARY
External M aster M ode EBU C LK
t1
H OLD
t2
t4
H LDA
t3
BREQ
t8
t7
External S lave M ode EBU C LK
t7
BREQ
t8
t5
H LDA
t6
t1
H OLD
t2
M C T 05324_m od
Figure 22
External Bus Arbitration Timing
Data Sheet
57
V 1.0, 2003-10
TC1910
PRELIMINARY SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Parameter SCLK period MTSR low/high from SCLK edge MRST setup to SCLK edge MRST hold from SCLK edge Symbol min. tSCLK t5 t6 t7 CC CC SR SR 40 15 15 2.0 Limit Values max. ns ns ns ns Unit
tSCLK
SCLK
(CON.PO,CON.PH=00 or 11)
0.5 VDD
0.9 VDD 0.1 VDD
t2
SCLK
(CON.PO,CON.PH=01 or 10)
t2
t4
t3
0.9 VDD 0.1 VDD
0.5 VDD
t3 t5
MTSR
State n-1 State n
t4
State n+1
t6
MRST
t7
Data valid
MCT04885
Data valid
Figure 23
SSC Master Mode Timing
Data Sheet
58
V 1.0, 2003-10
TC1910
PRELIMINARY Package Outlines
Figure 24
P-LBGA-208 Package
You can find all of our packages, sorts of packing and other in our Infineon Internet Page "Products": http://www.infineon.com/products *
Data Sheet 59 V 1.0, 2003-10
TC1910
PRELIMINARY
Data Sheet
60
V 1.0, 2003-10
((49))
http://www.infineon.com
Published by Infineon Technologies AG

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